Semiconductor devices are employed in various systems in a wide variety of applications. An important type of semiconductor device used as a memory is known as dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). The DRAM is extensively used for memory in computers and other electronic devices. A basic DRAM cell may include a capacitor and a transistor each formed in a semiconductor substrate. The capacitor stores a charge to represent a data value. The transistor allows the data value to be refreshed, read from, or written to the capacitor. FIG. 11 illustrates a conventional DRAM memory cell 200 including a capacitor 210 and a transistor 220. The capacitor 210 includes a first electrode 212 and a second electrode 214. The transistor 220 includes a source (or drain) 222 connected to the second electrode 214. The transistor 220 also includes a drain (or source) 224 connected to a bit line 232, as well as a gate 226 connected to a word line 230. The data value may be refreshed, read from or written to the capacitor 210 by applying appropriate voltages to the bit line 232 and/or the word line 230.
A series of DRAM memory cells is typically arranged in an array. More DRAM cells can be fit onto a chip by reducing the size of the capacitor and/or the transistor, thus resulting in greater memory capacity for the chip. One method of minimizing the size of a DRAM cell is to reduce the surface area of the device, which may be accomplished by vertically constructing the components, i.e., where a semiconductor device includes components formed in several layers. One method of performing vertical construction involves stacking layers of material that form the capacitor and/or the transistor on the surface of a semiconductor substrate. An alternative vertical construction method is to form components in a trench in the semiconductor substrate. For example, a dopant may be added to portion of the substrate surrounding the trench in order to form one of the electrodes, the xe2x80x9couter electrode,xe2x80x9d of the capacitor. A dielectric film may then be deposited along the sidewalls of the trench. Then, polycrystalline silicon, or xe2x80x9cpolysiliconxe2x80x9d (poly-Si) may be deposited on the dielectric film, acting as the second electrode, the xe2x80x9cinner electrodexe2x80x9d or xe2x80x9cstorage electrode,xe2x80x9d of the capacitor. Further processing steps may then be performed in order to finish fabricating the capacitor and other components of the memory cell, e.g., a buried strap connection to the transistor or connections to the bit line or word line of the memory cell.
As the surface area of a memory cell is made smaller and higher DRAM density is achieved, the trench region in which capacitors are formed may be reduced. Thus, the size of the trench typically, but not always, decreases as the memory capacity of the DRAM chip increases. As the size of the DRAM memory cell decreases, the capacitance of the capacitor becomes a critical parameter that can affect memory cell operation. Specifically, the capacitance needs to remain above a certain level in order for the capacitor to store charge effectively. Signal margin and retention time of the memory cell are directly affected by the capacitor""s storage ability. In particular, the capacitor may need to maintain a capacitance of at least 25 fF. If the capacitance falls significantly below this level, the charge of the capacitor may dissipate too rapidly and the data value stored by the memory cell may be lost. In order to avoid such a problem, the capacitance is preferably at least 30-35 fF.
Such a capacitance may be achieved through various techniques. In one technique, trenches may be formed relatively deep into the substrate (xe2x80x9cdeep trenchesxe2x80x9d), for example between 4-8 xcexcm below the substrate surface. This will permit the total size of the trench to remain the same, or even increase, when compared to a shallower but wider trench. Deep trenches having a small surface area are typically said to have a high aspect ratio. The xe2x80x9caspect ratioxe2x80x9d is the ratio of the depth of a trench compared to the width of the opening at the top of the trench. For example, memory cells fabricated as part of a 256 Mbyte DRAM chip may include capacitor trenches having an aspect ratio of between 10:1 and 20:1. This means that the depth of the trench walls is between 10 and 20 times greater than the width of the trench opening. In higher density DRAM chips, such as chips of 1 Gbyte or more, a typical deep trench aspect ratio may be on the order of 40:1 to 60:1 or higher. In such high aspect ratio situations, the trenches are typically very narrow. The very narrow trenches impact not only the thickness of the fill material of the inner electrode of the capacitor, but also how the fill material is formed in the trench. Thus, in order to properly fabricate a high aspect ratio deep trench capacitor, unconventional materials or processes may be required, which can increase the time and cost of manufacturing.
An alternative technique for increasing the capacitance of the capacitor is to form a xe2x80x9cbottlexe2x80x9d trench. Typically, a bottle trench is fabricated by first etching a standard trench shape, e.g., a vertical trench, in the semiconductor substrate. Then, the bottle shape may be created by widening a bottom portion of the trench. This may be accomplished by etching or a similar process. The width of the bottle shape may be limited by various parameters or physical dimensions of the memory cell. Therefore, a bottle trench may not be feasible in some situations.
Another technique for increasing capacitance is to fabricate a storage electrode with a xe2x80x9cgrainyxe2x80x9d surface. The grainy surface provides increased surface area and, hence, increased capacitance. Commonly, the grainy storage electrode will comprise a layer of doped poly-Si within a trench or in a stacked structure. A form of poly-Si having a grainy surface is hemispherical grain poly-Si (HSG). Annealing amorphous silicon in an ultra high vacuum condition forms HSG. One drawback of HSG is that in a trench capacitor design the granular structure is constrained by the dimensions of the trench sidewalls. Another drawback to the HSG process is the need for a selective HSG removal step from the collar portion of the DRAM cell. This is typically achieved using a top-down RIE process which suffers from poor recess control and therefore incomplete HSG removal. Remaining HSG grains can provide an electrical short between the buried plate and poly-Si fill, thus rendering the memory cell inoperable. Thus, HSG may be unsuitable for memory cell designs.
A need exists for improved capacitance in memory cells. A need also exists for methods of forming memory cells having improved capacitance. The present invention provides an capacitor structure having a sufficient capacitance by forming a micro-masking structure in the trench during fabrication.
In accordance with one aspect of the invention, a method of fabricating a semiconductor device is provided. A trench having sidewalls is formed in a semiconductor substrate. The method employs a micro-masking structure to increase the surface area of the sidewalls, which will in turn allow for more storage electrode material, hence a greater capacitance. First, the micro-masking structure is distributed along the sidewalls to expose some portions of the sidewalls while covering other portions of the sidewalls. Next, the exposed portions of the sidewalls are recessed to form a plurality of recesses, giving the sidewalls increased surface area. Finally, the micro-masking structure is removed.
Preferably, the micro-masking structure includes a mask and islands disposed over the mask. The mask may be grown on the sidewalls. The islands may be deposited using a CVD process. The CVD process is preferably an LPCVD process performed at a temperature of between 575xc2x0 C. to 800xc2x0 C. for between 1-30 minutes such that the islands are distributed across the mask.
In accordance with another aspect of the invention, a semiconductor device is provided including a semiconductor substrate and a capacitor. The capacitor is formed in the semiconductor substrate, and includes a trench, an outer electrode, a node dielectric and an inner electrode. The trench is defined by sidewalls having an exterior side facing the semiconductor substrate and an interior side remote from the semiconductor substrate. Recesses are formed along the sidewalls to provide increased surface area. The outer electrode substantially surrounds a lower portion of the sidewalls on the exterior side. The node dielectric lines the lower portion of the sidewalls on the interior side, including the recesses. The inner electrode substantially fills the trench.
Preferably, the recesses are formed along the sidewalls by applying a micro-masking structure to the sidewalls and etching portions of the sidewalls not covered by the micro-masking structure. The micro-masking structure preferably includes nitride islands formed over an oxide mask. The nitride islands preferably have a thickness below 40 xc3x85.
In accordance with another aspect of the invention, a method of fabricating a semiconductor device in a semiconductor substrate is provided. A first electrode having sidewalls is formed on top of the semiconductor substrate. A micro-masking structure is then distributed along the sidewalls to expose portions of the sidewalls while covering other portions of the sidewalls. The exposed portions are recessed to form a plurality of recesses such that the sidewalls have an increased surface area. The micro-masking structure is then removed. Next, a dielectric liner is formed over the first electrode, followed by a second electrode being formed over the dielectric liner. The first electrode, the dielectric liner and the second electrode comprise a stacked capacitor.
In accordance with yet another aspect of the invention, a semiconductor device is provided including a semiconductor substrate and a capacitor formed over the semiconductor substrate. The capacitor includes an inner electrode defined by sidewalls, which have a plurality of recesses formed therein. A node dielectric substantially lines the sidewalls, and an outer electrode substantially surrounds the node dielectric. The plurality of recesses provide increased surface area. The recesses are preferably formed using a micro-masking structure including nitride islands formed over an oxide mask. The nitride islands are preferably below 40 xc3x85 in thickness. Preferably, the semiconductor device includes a transistor electrically connected to the capacitor, the capacitor being formed over a portion of the transistor in a stacked configuration.
Semiconductor devices of the present invention and methods of fabricating a semiconductor device of the present invention provide capacitor structures having improved capacitance. The foregoing aspects, features and advantages of the present invention will be further appreciated when considered with reference to the following description of the preferred embodiments and accompanying drawings, wherein like reference numerals represent like elements.